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Constraining Designs for Synthesis and Timing Analysis Sridhar Gangadharan

Constraining Designs for Synthesis and Timing Analysis By Sridhar Gangadharan

Constraining Designs for Synthesis and Timing Analysis by Sridhar Gangadharan

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Summary

This book serves as a hands-on guide to timing constraints in integrated circuit design. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.

Constraining Designs for Synthesis and Timing Analysis Summary

Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC) by Sridhar Gangadharan

This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.

About Sridhar Gangadharan

Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, withtwo decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.

Sridhar Gangadharan is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.

Table of Contents

Introduction.- Synthesis Basics.- Timing Analysis and Constraints.- SDC Extensions through Tcl.- Clocks.- Generated Clocks.- Clock Groups.- Other Clock Characteristics.- Port Delays.- Completing Port Constraints.- False Paths.- Multi Cycle Paths.- Combinatorial Paths.- Modal Analysis.- Managing Your Constraints.- Miscellaneous SDC Commands.- XDC: Xilinx Extensions To SDC.

Additional information

NPB9781461432685
9781461432685
1461432685
Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC) by Sridhar Gangadharan
Sridhar Gangadharan
New
Hardback
Springer-Verlag New York Inc.
2013-05-07
226
N/A
Book picture is for illustrative purposes only, actual binding, cover or edition may vary.
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