Cart
Free US shipping over $10
Proud to be B-Corp

High Level Synthesis of ASICs under Timing and Synchronization Constraints David C. Ku

High Level Synthesis of ASICs under Timing and Synchronization Constraints By David C. Ku

High Level Synthesis of ASICs under Timing and Synchronization Constraints by David C. Ku


Summary

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design.

High Level Synthesis of ASICs under Timing and Synchronization Constraints Summary

High Level Synthesis of ASICs under Timing and Synchronization Constraints by David C. Ku

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers.
High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book.
Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model.
The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

Table of Contents

1. Introduction. 2. System Overview. 3. Behavioral Transformations. 4. Sequencing Graph and Resource Model. 5. Design Space Exploration. 6. Relative Scheduling. 7. Resource Conflict Resolution. 8. Relative Control Generation. 9. Relative Control Optimization. 10. System Implementation. 11. Experimental Results. 12. Conclusions and Future Work. References. Index.

Additional information

NPB9780792392446
9780792392446
0792392442
High Level Synthesis of ASICs under Timing and Synchronization Constraints by David C. Ku
New
Hardback
Springer
1992-05-31
294
N/A
Book picture is for illustrative purposes only, actual binding, cover or edition may vary.
This is a new book - be the first to read this copy. With untouched pages and a perfect binding, your brand new copy is ready to be opened for the first time

Customer Reviews - High Level Synthesis of ASICs under Timing and Synchronization Constraints