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VHDL Designer’s Reference Jean-Michel Berg

VHDL Designer’s Reference By Jean-Michel Berg

VHDL Designer’s Reference by Jean-Michel Berg


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Summary

The success of the introduction of VHDL in a company depends on solutions to many questions that should be answered months before the first line of code is written: • Why choose VHDL? • Which VHDL tools should be chosen? • How should the VHDL environment be customized? • What are the differences between VHDL and other competing HDLs?

VHDL Designer’s Reference Summary

VHDL Designer’s Reference by Jean-Michel Berg

too vast, too complex, too grand ... for description. John Wesley Powell-1870 (discovering the Grand Canyon) VHDL is a big world. A beginner can be easily disappointed by the generality of this language. This generality is explained by the large number of domains covered - from specifications to logical simulation or synthesis. To the very beginner, VHDL appears as a "kit". He is quickly aware that his problem may be solved with VHDL, but does not know how. He does not even know how to start. In this state of mind, all the constraints that can be set to his modeling job, by using a subset of the language or a given design methodology, may be seen as a life preserver. The success of the introduction of VHDL in a company depends on solutions to many questions that should be answered months before the first line of code is written: • Why choose VHDL? • Which VHDL tools should be chosen? • Which modeling methodology should be adopted? • How should the VHDL environment be customized? • What are the tricks? Where are the traps? • What are the differences between VHDL and other competing HDLs? Answers to these questions are organized according to different concerns: buying the tools, organizing the environment, and designing. Decisions taken in each of these areas may have many consequences on the way to the acceptance and efficiently use of VHDL in a company.

Table of Contents

1. Introduction. 2. VHDL Tools. 3. VHDL and Modeling Issues. 4. Structuring the Environment. 5. System Modeling. 6. Structuring Methodology. 7. Tricks and Traps. 8. M and VHDL. 9. VERILOG and VHDL. 10. UDL/I and VHDL. 11. Memo. 12. Index. List of Figures.

Additional information

NPB9780792317562
9780792317562
0792317564
VHDL Designer’s Reference by Jean-Michel Berg
New
Hardback
Springer
1992-05-31
455
N/A
Book picture is for illustrative purposes only, actual binding, cover or edition may vary.
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