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Leakage in Nanometer CMOS Technologies Siva G. Narendra

Leakage in Nanometer CMOS Technologies By Siva G. Narendra

Leakage in Nanometer CMOS Technologies by Siva G. Narendra


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Summary

Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles.

Leakage in Nanometer CMOS Technologies Summary

Leakage in Nanometer CMOS Technologies by Siva G. Narendra

Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles.

Also treated are the resulting effects so the reader understands the effectiveness of leakage power reduction solutions under these different conditions.

Case studies supply real-world examples that reap the benefits of leakage power reduction solutions as the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

Table of Contents

Taxonomy of Leakage: Sources, Impact, and Solutions.- Leakage Dependence on Input Vector.- Power Gating and Dynamic Voltage Scaling.- Methodologies for Power Gating.- Body Biasing.- Process Variation and Adaptive Design.- Memory Leakage Reduction.- Active Leakage Reduction and Multi-Performance Devices.- Impact of Leakage Power and Variation on Testing.- Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors.- Case Study: Leakage Reduction in the Intel Xscale Microprocessor.- Transistor Design to Reduce Leakage.

Additional information

NPB9780387257372
9780387257372
0387257373
Leakage in Nanometer CMOS Technologies by Siva G. Narendra
New
Hardback
Springer-Verlag New York Inc.
2005-11-17
308
N/A
Book picture is for illustrative purposes only, actual binding, cover or edition may vary.
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