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ASIC Design and Synthesis Vaibbhav Taraate

ASIC Design and Synthesis By Vaibbhav Taraate

ASIC Design and Synthesis by Vaibbhav Taraate

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Summary

This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.

ASIC Design and Synthesis Summary

ASIC Design and Synthesis: RTL Design Using Verilog by Vaibbhav Taraate

This book describes simple to complex ASIC design practical scenarios using Verilog.Itbuilds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, thecontentsprovide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance.Italso covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

About Vaibbhav Taraate

Vaibbhav Taraate is an entrepreneur and mentor at 1 Rupee S T. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog , VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.


Table of Contents

Chapter 1. Introduction.- Chapter2. Design using CMOS.- Chapter3. ASIC design synthesis for combinational design (RTL using VHDL).- Chapter4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL).- Chapter5. ASIC Design and synthesis of sequential logic (RTL using VHDL).- Chapter6. ASIC design guidelines.- Chapter7. ASIC RTL Verification.- Chapter8. FSM using VHDL and synthesis.- Chapter9. ASIC design improvement techniques.- Chapter10. ASIC Synthesis using Synopsys DC.- Chapter11. Design for Testability.- Chapter12. Static timing analysis.- Chapter13. Multiple Clock domain designs.- Chapter14. Low power ASIC design.- Chapter15. ASIC Physical design.

Additional information

NPB9789813346413
9789813346413
9813346418
ASIC Design and Synthesis: RTL Design Using Verilog by Vaibbhav Taraate
Vaibbhav Taraate
New
Hardback
Springer Verlag, Singapore
2021-01-07
330
N/A
Book picture is for illustrative purposes only, actual binding, cover or edition may vary.
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