(NOTE:
Each chapter begins with a Summary and ends with a Summary, Breakout Exercises and Problems).
1. Introduction. Why Use VHDL? Shortcomings. Using VHDL for Design Synthesis. Design Tool Flow. Our System. Font Conventions.
2. Programmable Logic Primer. Introduction. Why Use Programmable Logic? What Is a Programmable Logic Device? Simple PLDs. What Is a CPLD? What Is an FPGA? PREP Benchmarks. Future Direction of Programmable Logic.
3. Entities and Architectures. A Simple Design. Design Entities. Identifiers, Data Objects, Data Types, and Attributes. Common Errors.
4. Creating Combinational and Synchronous Logic. Design Example. Combinational Logic. Synchronous Logic. Designing a FIFO. Common Errors. Test Benches.
5. State Machine Designs. A Simple Design Example. A Memory Controller. Mealy State Machines. Additional Design Considerations.
6. Hierarchy in Large Designs. Case Study: The AM2901. Case Study: A 100BASE--T4 Network Repeater.
7. Functions and Procedures. Functions. Procedures. About Subprograms.
8. Synthesis and Design Implementation. Design Implementation: An Example. Synthesis and Fitting. CPLDs: A Case Study. FPGAs: A Case Study.
9. Optimizing Datapaths. Pipelining. Resource Sharing. Magnitude Comparators. Fast Counters.
10. Creating Test Benches. Approaches to Writing Test Benches. Overloaded Read and Write Procedures.
Afterword. Review. Where To Go from Here. Appendix A: Viewing On-line Documentation and Installing Warp. Appendix B: Reserved Words. Appendix C: STD_logic_1164 Package. Appendix D: Quick Reference Guide. Glossary. Bibliography. Index. 