Name: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies By Andrei Pavlov
SKU: 9789048178551
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Summary

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test by Andrei Pavlov

The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.

About Andrei Pavlov

Prof. Sachdev has authored several successful books with Springer

Foreword. Preface. Acronyms. 1. INTRODUCTION AND MOTIVATION. 1.1 Motivation. 1.2 SRAM in the Computer Memory Hierarchy. 1.3 Technology Scaling and SRAM Design and Test. 1.4 SRAM test economics. 1.5 SRAM Design and Test Tradeoffs. 1.6 Redundancy. 2. SRAM CIRCUIT DESIGN AND OPERATION. 2.1 Introduction. 2.2 SRAM block structure. 2.3 SRAM cell design. 2.4 Cell layout considerations. 2.5 Sense Amplifier and Bit Line Precharge-Equalization. 2.6 Write Driver. 2.7 Row Address Decoder and Column MUX. 2.8 Address Transition Detector. 2.9 Timing Control Schemes. 2.10 Summary. 3. SRAM CELL STABILITY: DEFINITION, MODELING AND TESTING. 3.1 Introduction. 3.2 Static noise margin of SRAM cells. 3.3 SNM Definitions. 3.4 Analytical expressions for SNM calculations. 3.5 SRAM cell stability sensitivity factors. 3.6 SRAM cell stability fault model. 3.7 SRAM Cell Stability Detection Concept. 3.8 March tests and stability fault detection in SRAMs. 3.9 Summary. 4. TRADITIONAL SRAM FAULT MODELS AND TEST PRACTICES. 4.1 Introduction. 4.2 Traditional fault models. 4.3 Traditional SRAM test practices. 4.4 Summary. 5. TECHNIQUES FOR DETECTION OF SRAM CELLS WITH STABILITY FAULTS. 5.1 Introduction. 5.2 Classification of SRAM cell stability test techniques. 5.3 Passive SRAM Cell Stability Test Techniques. 5.4 Active SRAM Cell Stability Test Techniques. 5.5 Summary. 6. SOFT ERROR IN SRAMs: SOURCES, MECHANISM AND MITIGATION TECHNIQUES. 6.1 Introduction. 6.2 Soft Error Mechanism. 6.3 Sources of Soft Errors. 6.4 Soft Errors and Defects in the Pull-Up Path of a Cell. 6.5 Soft Error Mitigation Techniques. 6.6 Leakage-Reduction Techniques and the SER. 6.7 Summary. References. Index.

Additional information

Sku

NLS9789048178551

ISBN 13

9789048178551

ISBN 10

904817855X

Title

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test by Andrei Pavlov

Author

Andrei Pavlov

Series

Frontiers in Electronic Testing

Condition

New

Binding type

Paperback

Publisher

Springer

Year published

2010-10-28

Number of pages

194

Prizes

N/A

Cover note

Book picture is for illustrative purposes only, actual binding, cover or edition may vary.

Note

This is a new book - be the first to read this copy. With untouched pages and a perfect binding, your brand new copy is ready to be opened for the first time

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Andrei Pavlov

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies by Andrei Pavlov

Summary

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Summary

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test by Andrei Pavlov

About Andrei Pavlov

Table of Contents

Additional information

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